This invention pertains to the field of digital circuits, and more particularly, to a power-on reset circuit for a digital circuit, and a semiconductor device including the same.
When a power supply voltage is turned on, to be supplied to a digital circuit (such as a memory circuit), there is a period of time necessary for the power supply voltage to ramp-up to its final (steady-state) value and stabilize. If the power supply voltage is applied to the digital circuit during this ramp-up period, then an unpredictable and undesired operation of the digital circuit may occur, including possible latch-up problems, etc. Such problems may not recover once the power supply voltage reaches its final value and stabilizes.
Accordingly, it is common to provide a power-on reset circuit for a digital circuit to provide a reset signal to the digital circuit to reset the digital circuit to a known state once the power supply voltage reaches a desired threshold voltage level. Such a power-on reset circuit typically includes a delay circuit connected to the power supply voltage to provide a delayed reset signal that will only reach a reset threshold voltage level to reset the digital circuit(s) after the power supply voltage reaches a desired power supply voltage threshold level.
FIG. 1 illustrates the input stage 100 of a conventional power-on reset circuit. The input stage 100 includes first and second PMOS transistors 110 and 120, resistor 130, and capacitor 140. The power supply voltage is indicated as VSS and the output signal is indicated as VOUT. The input stage 100 is followed by a second stage, typically a Schmidt trigger, to provide a power-on reset signal to the remaining digital circuits as will be described in more detail below.
The input stage 100 can be modeled as a current source connected in series with the capacitor 140. The current source is established by the current mirror relationship of first and second PMOS transistors 110 and 120. The output signal VOUT is a ramp signal whose slope is determined by the current of the current source and the capacitance of the capacitor 140. The VOUT ramp signal is provided to a second stage, typically a Schmidt trigger, having a threshold to convert the VOUT ramp signal into a VRESET pulse signal having a sharp transition edge.
Because of the current mirror, a power-on reset circuit having the input stage 100 can produce a reset signal VRESET with a much higher delay for the same values of resistor 130 and capacitor 140 compared to a power-on reset circuit whose input stage is a simple RC delay circuit. For example, if the current mirror scales down the current through the capacitor 140 by a factor of ten (10), then the resulting delay will be scaled up by about the same factor of 10 compared to an RC delay circuit having the same size capacitor. This can be especially beneficial when the power-on reset circuit having the input stage 100 is incorporated into a digital integrated circuit (IC) device where space considerations are very important.
Unfortunately, there are problems with the conventional power-on reset circuit having the input stage 100. For example, once the power-on reset circuit has performed its principle function (providing a delayed reset signal upon power-up), there remains a DC static current through the circuit by means of the current through the current mirror transistor 110 and the resistor 130. As a result, the power-on reset circuit will needlessly consume and waste power even in its xe2x80x9cstandbyxe2x80x9d mode of operation.
One solution to the above-mentioned problem has been disclosed in U.S. Pat. No. 6,052,006. However, the disclosed solution requires more than five additional transistors to stop the current flow through the power-on reset circuit once the circuit has performed its principle function.
Accordingly, it would be desirable to provide an improved power-on reset circuit, and in particular, a power-on reset circuit having an improved input stage. It would also be desirable to provide a power-on reset circuit that consumes very little, if any, power in a standby mode. It would be further desirable to provide a power-on reset circuit that eliminates static DC current flow through the circuit during a standby mode. It would be still further desirable to provide a power-on reset circuit that includes a less complicated means of eliminating static DC current flow through the circuit during a standby mode. The present invention is directed to addressing one or more of the preceding concerns.
In one aspect of the invention, a power-on reset circuit comprises a current mirror connected to a first power supply voltage, a capacitor receiving current from the current mirror, and current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the capacitor reaches a threshold voltage level.
In another aspect of the invention, a semiconductor device includes a digital circuit having a reset input and power-on reset circuit providing a reset signal to the reset input, the power-on reset circuit comprising a current mirror connected to a first power supply voltage, a first capacitor receiving current from the current mirror, and current shutoff means connected between the current mirror and a second power supply voltage, the current shutoff means being adapted to shut off the current received by the first capacitor when a voltage across the capacitor reaches a threshold voltage level.